1. Field of the Invention
This invention relates to a sense circuit for use in a semiconductor memory of multi-bit configuration or the like, and more particularly to a sense circuit constituted by use of MOSFETs.
2. Description of the Related Art
Conventionally, a latch sense circuit of the construction shown in FIG. 1 and current mirror type sense circuit of the construction shown in FIG. 2 are known in the art as a sense circuit for use in a semiconductor memory.
The latch sense circuit shown in FIG. 1 includes two CMOS inverters I1 and I2 whose input terminals are connected to a pair of bit lines BL and BL. The input and output terminals of COMS inverter I1 are respectively connected to the output and input terminals of CMOS inverter I2. The sense circuit is activated when sense circuit activation signal SE is set at "H" level and inverted signal SE of the sense circuit activation signal is set at "L" level, and at this time the difference in potential between paired bit lines BL and BL is amplified by the sense circuit.
The latch sense circuit should not be activated until the difference in potential between paired bit lines BL and BL becomes sufficiently large. Otherwise, data may be erroneously read out. In order to prevent the erroneous readout operation, it is necessary to take a sufficiently long time before the activation, thereby lowering the sense speed.
When the latch sense circuit finished the sensing operation, bit lines BL and BL are set at the power source potential or the ground potential and thus the potential amplitude of the bit line potential becomes large. If the parasitic capacitance associated with the bit line is large or the cycle time is short, the power consumption caused by charging the bit line becomes large.
The current mirror type sense circuit shown in FIG. 2 includes two input N-channel MOSFETs N21 and N22, current limiting N-channel MOSFET N23 and two P-channel MOSFETs P21 and P22 used as the current mirror load.
In the current mirror type sense circuit, the input terminals thereof are connected to a pair of bit lines BL and BL. When sense circuit activation signal SE is set at "H" level, current limiting MOSFET N23 is turned on and the current mirror type sense circuit is activated to derive data corresponding to the difference in potential between the paired bit lines at output node DO. In this case, the amplification of the input signal is not effected, that is, the input potential is not changed over a full variation range of the power source voltage. As a result, the power consumption caused by charging and discharging the bit line can be suppressed to a minimum.
However, since the sense speed of the current mirror type sense circuit can be determined by current flowing in current limiting MOSFET N23, it is necessary to supply current of more than 0.3 mA, for example, in each sense circuit in order to sense the potential difference of the bit lines at a high speed. Therefore, in order to effect the simultaneous readout operation for a semiconductor memory of 200 bits, for example, a power of 0.3 W is dissipated only in the sense circuit if power source voltage VDD is 5 V. Therefore, the number of bits which can be simultaneously read is limited because the power consumption is limited. That is, in a semiconductor memory in which a large number of bits, for example, 500 bits are simultaneously read out, the above current mirror type sense circuit cannot be used.